Computer Systems: A Programmer's Perspective (Global Edition): The Road to Execution: Understanding the Compiler Driver

The Orchestrator: The Compiler Driver

Think of the Compiler Driver (like GCC) as a grand conductor. It automates the complex transformation from human-readable source code to a binary executable. This journey, the Road to Execution, begins at Compile time and spans into Load time and Run time.

By utilizing Separate compilation, the driver processes main.c and sum.c independently. Changes in one module don't require the entire project to be re-translated—only the modified file is passed through the preprocessor (cpp), compiler (cc1), and assembler (as) before the Linker (ld) merges the resulting Relocatable Object Files.

Efficiency & The Memory Hierarchy

The Linker’s layout decisions for grid[0][0] or src[0][0] directly impact Throughput and Latency. By aligning data into a 32-byte cache line, the driver facilitates a Stride-1 reference pattern, minimizing Cold misses and avoiding Column-wise scan evictions. In advanced high-performance code, Unrolled loop parallelism ($4 \times 4$ unrolled loop) further hides Main memory to Cache mapping delays by optimizing clock frequency cycles (0x32, 0x1, 0x4, 0x51).

TERMINAL bash — 80x24

> Ready. Click "Run" to execute.

QUESTION 1

Which component of the compiler driver is responsible for generating the assembly file (/tmp/main.s)?

The preprocessor (cpp)

The compiler (cc1)

The assembler (as)

The linker (ld)

QUESTION 2

What is a primary benefit of 'Separate Compilation'?

It makes the final executable run faster.

It allows modifications to one file without re-translating others.

It automatically unrolls all loops to 4x4.

It eliminates the need for a linker.

QUESTION 3

How does a Stride-1 reference pattern affect the L1 cache?

It causes column-wise scan evictions.

It maximizes hit rates by utilizing spatial locality.

It bypasses the cache to reduce latency.

It increases the number of cold misses to 100%.

QUESTION 4

What happens at 0x064C if the linker places a multi-byte integer across a 32-byte cache boundary?

The compiler driver automatically fixes it at run time.

The L1 cache throughput is maximized.

A potential drop in hit rates and increased latency occurs.

The assembler produces a relocatable error.

QUESTION 5

The hex representations 0x32, 0x1, 0x4, and 0x51 in the theory likely represent:

The binary tags for the L2 cache.

Clock frequency stalls or memory fetch latencies.

The sequence of registers used in a 4x4 unroll.

The static library identifiers.

Case Study: Memory Hierarchy & Hit Rates

Applying Figure 6.48 logic to cache performance

You are analyzing the performance of a program that transposes a matrix using two arrays: src and dst. Both are stored in memory addresses similar to 0x064C, 0x064D, 0x064E, and 0x064F. The system uses a 32-byte cache line. You must calculate how the driver's linking stage and the memory access pattern interact.

Based on Figure 6.48, what is the hit rate for the dst and src arrays when the cache is 32 bytes and large enough to hold both arrays?

Solution:
Assuming 4-byte integers and a 32-byte cache block, there are 8 integers per cache line (32 / 4 = 8). If the cache is large enough to hold both arrays, conflict and capacity misses are eliminated, leaving only cold misses. For a Stride-1 access pattern (reading row by row), the first access to a block is a miss, and the following 7 accesses are hits. Therefore, the hit rate for both arrays is 7/8, or 87.5%.

If the code uses a column-wise scan instead of Stride-1, how does this affect the 'Cache tag' and 'Cache set index' usage?

Solution:
A column-wise scan increases the stride between consecutive accesses. This likely means every access jumps to a different cache set index or causes a tag mismatch, resulting in 0% hit rates (all misses) if the matrix is larger than the cache, as the hardware must evict lines before they can be reused.